Hardware Design

The hardware chapters progress from the bill of materials through pin-level wiring, address generation, physical construction, buffering, and final bus isolation. For a first build, read the inventory and construction basics, then follow the phased implementation plan. Consult the other hardware chapters when a phase refers to them; their chapter order is not the chip-installation order.

Chapter	Purpose
0. Project inventory	Parts, passive components, power distribution, and required bench equipment
1. Reference pin mapping	Authoritative IC pin maps, signal ownership, and logic-domain checks
2. Address interface	Current 128 KiB SRAM address map, bank select, Z80-assisted loading, and four-bit port monitoring
3. Physical construction	Breadboard topology, socket placement, and jumper routing
4. Output buffer	AHCT244 channel allocation and enable behavior
5. Bus isolation	Address, data, and control transceiver operating modes

There are two four-layer PCB designs: a hand-assembled DIP / through-hole board and a compact, JLC-assembled partial-SMT board. They use different packages, SRAM parts and BOMs. Each board's mechanical assembly and 20 MHz qualification are separate from the breadboard implementation sequence.

The instrument procedures are cross-cutting qualification references rather than additional hardware chapters. Use the RIGOL DHO814 capture plan for analogue integrity and exact timing, and the DSLogic Plus capture plan for bus-wide digital state and event ordering. Individual implementation pass gates name the captures required at each phase.