DreamSourceLab DSLogic Plus Capture Plan¶

A logic analyser is optional for building the board. Use one to investigate bus activity and capture digital signal ordering; use a scope for voltage and analogue timing measurements.

Purpose and instrument limits¶

The DSLogic Plus proves simultaneous digital state, event ordering, bus values, and control sequencing. It complements the RIGOL DHO814: the logic analyzer answers what happened and in what order, while the oscilloscope proves voltage margin, rise/fall time, ringing, overshoot, and close analogue timing. Never use a logic-analyzer HIGH or LOW display as proof that a receiving device's datasheet voltage limits were met.

A displayed bus value is only as correct as the channel mapping: label the channels before capture and put bit 0 at the least-significant position. The analyzer samples rather than recording every instant; at 100 MHz, samples are 10 ns apart, so a shorter pulse may be missed. A clean-looking digital trace is not proof that the analog waveform has no glitch.

The official DSLogic Plus data sheet specifies:

Property	DSLogic Plus limit
Digital channels	16, CH0-CH15
Buffer Mode sample rate	400 MHz / 4 channels, 200 MHz / 8 channels, 100 MHz / 16 channels
Stream Mode sample rate	100 MHz / 3 channels, 50 MHz / 6 channels, 25 MHz / 12 channels, 20 MHz / 16 channels
Hardware memory	256 Mbits
Buffer depth without RLE	256 Mbits divided by enabled channel count
Maximum stream depth	16G samples
Input threshold	0-5 V, adjustable in 0.1 V steps
Input impedance	250 kOhm in parallel with approximately 13 pF
Protected CH0-CH15 range	-30 V to +30 V with the supplied fly wires
100 MHz sample interval	10 ns; sampling and threshold uncertainty limit edge timing

Use 16-channel, 100 MHz Buffer Mode for the complete address bus. At the board’s 20 MHz clock this gives only five samples per period, below the 10× sampling recommendation for phase-sensitive measurements. It is useful for bus values and coarse ordering, but cannot prove tight setup/hold margins. Use fewer channels at a higher sample rate or the scope for detailed timing.

Sixteen-channel Stream Mode runs at 20 MHz: only one sample per 20 MHz clock period. Reserve it for slow state/fault searches, not 20 MHz timing evidence.

Safety and connection preparation¶

Install the current DSView release from the DreamSourceLab download page. Connect DSLogic Plus directly to a reliable USB port. Open DSView and require the hardware indicator to turn green and the device selector to identify DSLogic Plus before attaching it to the circuit.
The probe grounds are connected through USB to the host computer ground. Connect them only to the SBC's common GND. Never attach a ground lead to +3.3 V, +5 V, a signal, or a floating/hot DUT. If the host is mains-grounded, DSLogic ground is earth-referenced.
Power off the SBC before attaching or moving clips. Connect ground leads first, then signal leads. Remove signal leads first when disconnecting.
Use the supplied shielded fly wires. Each active channel has an independent ground return; connect those returns to nearby common-GND points. The Z80 runs at 20 MHz with fast edges, so use the guide’s high-frequency connection method rather than one long shared ground lead.
Probe the physical destination pin listed below, not a distant jumper end. Sixteen inputs add meaningful capacitive loading to a solderless breadboard. Recheck operation at 1 MHz after connecting each group, and do not stack a scope probe on the same node unless that combined loaded condition is the test being qualified.
Do not connect CK, TI, or TO for the standard project captures. CK and TI are limited to the 0-3.3 V domain; attaching either to a 5 V Z80 signal violates the hardware data sheet. CH0-CH15 provide every trigger used here.

Baseline DSView configuration¶

Press O or open Options. Select Logic Analyzer and Buffer Mode, with Upload captured data as the stop option.
Select Use 16 Channels (Max 100 MHz), enable CH0-CH15, set Sample Rate = 100 MHz, and begin with Sample Duration = 100 ms. The official maximum at 100 MHz with 16 channels is approximately 167.77 ms.
Set Filter Targets = None. The 1 Sample Clock filter suppresses pulses shorter than one sample interval and must not be used as pass evidence.
Disable RLE Compress for baseline qualification so capture depth is fixed and reproducible. A separately labelled RLE capture may be used to search for sparse events, but it does not replace the baseline capture.
Set the single device threshold for the selected group: 3.5 V for Group A, 2.2 V for Group B, or 1.6 V for mixed 3.3 V/TTL Groups C and D. These thresholds make transitions visible at useful digital decision levels; the DHO814 still proves device-specific $V_{IH}$/$V_{IL}$ margins.
Select Single Capture and Normal Capture. Do not use Instant Capture as pass evidence because it ignores trigger settings. Repetitive Capture is useful only as additional evidence for repeatable events.
Press T to open Trigger. Use Simple Trigger unless a scenario below requests a bus pattern. Clear every stale channel condition first: multiple Simple Trigger conditions are ANDed at the same sample point.
Start with the trigger position at 30% to retain the cause and more post-trigger response. Use 50% when equal pre/post context is useful. Stream Mode fixes the trigger close to the start and is not used for these gates.
Rename every channel to the signal shown in its group before capture. Use cursors and edge snap to measure ordering; record the sample count between relevant edges as well as the displayed time.
Save the complete .dsl capture and DSView session, export a VCD or raw CSV, and save a PNG screenshot. Include phase, clock rate, stimulus, group, threshold, sample rate, duration, filter, RLE state, and trigger in the name.

Group A: complete SRAM address bus¶

Use threshold 3.5 V. This group proves all address bits simultaneously at the SRAM receiver pins.

DSLogic channel	Signal	Physical probe point
CH0	A0	SRAM pin 12
CH1	A1	SRAM pin 11
CH2	A2	SRAM pin 10
CH3	A3	SRAM pin 9
CH4	A4	SRAM pin 8
CH5	A5	SRAM pin 7
CH6	A6	SRAM pin 6
CH7	A7	SRAM pin 5
CH8	A8	SRAM pin 27
CH9	A9	SRAM pin 26
CH10	A10	SRAM pin 23
CH11	A11	SRAM pin 25
CH12	A12	SRAM pin 4
CH13	A13	SRAM pin 28
CH14	A14	SRAM pin 3
CH15	A15	SRAM pin 31

Group B: memory data and controls¶

Use threshold 2.2 V. Group B correlates the complete byte with the CPU and SRAM control cycle. The analogue scope captures remain responsible for proving the SRAM's stricter write-data HIGH margin.

DSLogic channel	Signal	Physical probe point
CH0-CH7	D0-D7 in ascending order	SRAM pins 13, 14, 15, 17, 18, 19, 20, 21
CH8	CLK	Z80 pin 6
CH9	MREQ#	Z80 pin 19
CH10	RD#	Z80 pin 21
CH11	WR#	Z80 pin 22
CH12	SRAM CE#	SRAM pin 22
CH13	SRAM OE#	SRAM pin 24
CH14	SRAM WE#	SRAM pin 29
CH15	M1#	Z80 pin 27

Optional DSView Z80 decoder cross-check¶

After preserving the raw Group B capture, add DSView's Z80 protocol decoder and bind D0-D7 to CH0-CH7, M1# to CH15, RD# to CH10, WR# to CH11, and optional MREQ# to CH9. Leave IORQ# and A0-A15 unbound for this group. The decoder can annotate opcode fetches and memory read/write bytes, but it cannot report the full address and must not replace manual inspection of the raw controls. Group C remains authoritative for trapped I/O, and Group A remains authoritative for the complete address bus.

Group C: trapped I/O and data-path exclusion¶

Use threshold 1.6 V. Repeat for IN with RD# on CH10 and OUT with WR# on CH10. Data-path exclusion is a firmware rule, not a hardware interlock. In Phases 9-10 every cycle completes in PIO: OUTs with a free-running clock, INs with exactly two clocks after WAIT release and CLK held LOW until U9 is isolated. Capture them as separate categories and confirm on raw captures that U9 disables before CLK resumes into the next opcode fetch. Capture A16 separately when checking OUT 07h bank switching, following the PIO reference.

DSLogic channel	Signal	Physical probe point
CH0-CH7	D0-D7 in ascending order	SRAM pins 13, 14, 15, 17, 18, 19, 20, 21
CH8	CLK	Z80 pin 6
CH9	IORQ#	Z80 pin 20
CH10	RD# for IN; WR# for OUT	Z80 pin 21; repeat at pin 22
CH11	WAIT#	Z80 pin 24
CH12	IO_RELEASE	Pico GP9, header pin 12
CH13	PICO_DATA_UP_OE# request	Pico GP6, header pin 9
CH14	Pico-to-bus transceiver OE#	SN74AHCT245 pin 19
CH15	Bus-to-Pico transceiver OE#	SN74LVC245 pin 19

Group D: SRAM boot inhibit and control propagation¶

Use threshold 1.6 V. This mixed group follows CPU controls through the AHCT244 and HCT32 to SRAM, and checks injected loading and flash quiescence.

DSLogic channel	Signal	Physical probe point
CH0	RESET#	Z80 pin 26
CH1	BUSREQ#	Z80 pin 25
CH2	BUSACK#	Z80 pin 23
CH3	Z80 MREQ#	Z80 pin 19
CH4	Z80 RD#	Z80 pin 21
CH5	Z80 WR#	Z80 pin 22
CH6	Buffered MREQ# / SRAM CE#	AHCT244 pin 12
CH7	Buffered RD#	AHCT244 pin 7
CH8	Buffered WR# / SRAM WE#	AHCT244 pin 9
CH9	SRAM CE#	SRAM pin 22
CH10	SRAM OE#	SRAM pin 24
CH11	SRAM WE#	SRAM pin 29
CH12	BOOT_READ_DISABLE	Pico GP5, header pin 7
CH13	PICO_DATA_UP_OE# request	Pico GP6, header pin 9
CH14	DATA_DOWN_OE#	Pico GP7, header pin 10
CH15	CLK	Z80 pin 6

Trigger and expected outcomes¶

Purpose	Group and trigger	Expected result
Address integrity	Group A. Set all 16 Simple Trigger levels to match 0000, FFFF, 5555, or AAAA; all conditions are ANDed. Repeat for each fixed pattern and trigger on 0000 for walking/CPU-read sequences.	Each sampled test address matches its expected pattern; walking-one/zero patterns select the intended bit, and no address transition occurs during the active sampling interval of a memory cycle. Repeat at every qualified clock rate.
Opcode fetch	Group B, CH15 M1# falling.	M1#, MREQ#, RD#, CE#, and OE# assert in the expected active-LOW sequence; WE# remains HIGH and D0-D7 contain the fetched opcode before the Z80 sampling edge.
SRAM read	Group B, CH10 RD# falling with CH9 MREQ# LOW.	CE# and OE# assert once, WE# remains HIGH, and all eight data bits settle to the expected byte before the sampling edge. No extra control transition is permitted.
SRAM write	Group B, CH11 WR# falling with CH9 MREQ# LOW.	D0-D7 meet the SRAM’s setup/hold requirements around write completion; CE# and WE# assert once and OE# remains HIGH. DSLogic screens pulse presence and ordering only; the DHO814 must prove the exact 45 ns minimum WE# LOW width.
Reset and restart	Group D, CH0 RESET# rising, trigger position 30%.	RESET# was LOW for six complete clocks. Injection starts with inhibit HIGH after the two exit clocks. Normal restart has both data paths isolated and inhibit LOW; CPU controls alone operate SRAM. Verify real reset-exit phase before accepting the cycle model.
Flash quiescence	Group D, CH2 BUSACK# falling for acquisition; repeat rising for release.	BUSREQ# falls before BUSACK#. CPU address/control outputs float; pulls make SRAM controls inactive. Pico does not drive memory. Trap is armed before BUSREQ# release.
Injected loading	Group D, CH12 inhibit and CH4 RD# edges.	SRAM OE# stays HIGH during injected instructions. It falls only for a deliberate SRAM read, with Pico output isolated. SRAM WE# follows CPU writes, never a Pico-generated write pulse.
Trapped IN	Group C with RD# on CH10; trigger CH9 IORQ# falling.	WAIT# falls before sampling. Only AHCT245 OE# falls; the Pico supplies the reply byte. GP9 releases WAIT after preload. Phases 6-8: slow clocks complete the cycle. Phases 9-10: exactly two 20 MHz clocks (TW, T3), then CLK stays LOW. In both, both OEs are HIGH and GP9 LOW before the execution clock resumes into the next fetch.
Trapped OUT	Group C with WR# on CH10; trigger CH9 IORQ# falling.	WAIT# falls first. Only LVC245 OE# falls; the Pico samples the CPU byte. GP9 releases WAIT. Phases 6-8: stepped completion isolates/rearms before execution resumes. Phases 9-10: CLK free-runs after release; isolation/rearm follows IORQ# rising. The two OE# signals are never LOW together.

For the final frequency claim, save Group A, B, C-IN, C-OUT, and D captures at each tested rate. The separate groups must use the same firmware build, clock rate, and deterministic stimulus. A 16-channel DSLogic Plus cannot establish simultaneous whole-address, whole-data, and control ordering in one acquisition; do not imply otherwise in qualification records.