Phase 3 - Control and Port Monitor

VS Code tasks

Choose Tasks: Run Task in the Z80ROMlessSBC workspace.

Diagnostic	Build task	Deployment task
Phase 3 control inputs	Build Pico - Phase 3 control inputs	Flash Pico - Phase 3 control inputs

Deployment tasks force-update without checking the previous firmware phase. Complete this phase's hardware prerequisites and save work before flashing. See Pico tools.

Tick setup items when complete and tests only after recording the measured result. Progress is saved in this browser; ticks are not automatic verification.

Prerequisite: Phase 2. Install: U7 SN74LVC244AN only; Z80/SRAM remain absent. No address expander is fitted.

Wiring - Control and Port Monitor

U7 is the SN74LVC244AN eight-channel input buffer, powered from +3.3 V.

Disconnect external power and USB; keep U7 out of its socket until wiring checks pass. CPU and SRAM remain absent. Tick each channel after checking both wires at the actual socket contacts and Pico pins, and isolation from adjacent pins. Pico pin numbers below are physical pin positions, not GPIO numbers. See the Pico header reference.

Done	Signal	Z80 socket → U7 LVC244 input	U7 LVC244 output → Pico pin
	BUSACK#	Z80 pin 23 → U7 pin 2	U7 pin 18 → Pico pin 1 (GP0)
	IORQ#	Z80 pin 20 → U7 pin 4	U7 pin 16 → Pico pin 2 (GP1)
	RD#	Z80 pin 21 → U7 pin 6	U7 pin 14 → Pico pin 32 (GP27)
	WR#	Z80 pin 22 → U7 pin 8	U7 pin 12 → Pico pin 34 (GP28)
	A0	Z80 pin 30 → U7 pin 11	U7 pin 9 → Pico pin 24 (GP18)
	A1	Z80 pin 31 → U7 pin 13	U7 pin 7 → Pico pin 25 (GP19)
	A2	Z80 pin 32 → U7 pin 15	U7 pin 5 → Pico pin 26 (GP20)
	A4	Z80 pin 34 → U7 pin 17	U7 pin 3 → Pico pin 27 (GP21)

Done	Check
	Verify existing U7 connections: pins 1/10/19 directly to common GND, pin 20 to Pico-derived +3.3 V, not +5 V, and C5, 100 nF, nearby between +3.3 V and GND
	Install U7: with external power and USB disconnected, confirm continuity, no adjacent-pin shorts and correct pin-1 orientation before insertion

Never connect the 5 V Z80 signals directly to the Pico; route them through U7.

The four monitored bits provide 16 distinct I/O ports. See I/O ports and services for why A4 is monitored but A3 is not, fixed terminal/disk assignments and the Phase 9/10 shared service allocation.

Firmware and Tests

Build z80_stage03_control_inputs; UF2: build/src/stage03_mcp23s17/z80_stage03_control_inputs.uf2. Maintained application.

s samples BUSACK/IORQ/RD/WR and port. With CPU absent and pulls fitted, controls are HIGH and port is 17.

Pull each input LOW through a temporary 1 kOhm resistor; confirm only the matching GPIO/decoded bit changes and U7 outputs remain in the 3.3 V domain. Never short output pins to a rail.

Pull IORQ LOW and verify WAIT LOW. Type w to raise IO_RELEASE: WAIT must rise without either data OE becoming active.

Type x to rearm WAIT, then remove the temporary pull. This tests WAIT independently of data direction.

Pass Gate

• All eight input routes correct.
• WAIT release works with data paths disabled.
• Decoded address bits match address & 0x17, not a full 8-bit decode.

Maintained Source

The complete application below is included from the repository at documentation build time, not copied into this page.

Phase 3 application - src/stage03_mcp23s17/main.c

#include <stdio.h>
#include "pico/stdlib.h"
#include "z80sbc/bus.h"
#include "z80sbc/pins.h"
#include "z80sbc/supervisor.h"
int main(void) {
  z80_safe_startup();
  stdio_init_all();
  printf("\nStage 3: buffered control and port inputs; CPU absent\n");
  printf("s=sample inputs, w=release WAIT, x=safe restore\n");
  while (true) {
    int command = getchar_timeout_us(0);
    if (command == 's')
      printf("port=%02x BUSACK#=%u IORQ#=%u RD#=%u WR#=%u\n",
             z80_port_bus_sample(), gpio_get(PIN_BUSACK_N),
             gpio_get(PIN_IORQ_N), gpio_get(PIN_RD_N), gpio_get(PIN_WR_N));
    else if (command == 'w') gpio_put(PIN_IO_RELEASE, 1);
    else if (command == 'x') z80_safe_startup();
    tight_loop_contents();
  }
}