Appendix A: Terms and Abbreviations

This glossary explains the recurring terminology used in this document. Signal names ending in # are active LOW: for example, RESET# is asserted (active) at 0 V and deasserted (inactive) at a valid HIGH voltage. An overbar or _N suffix in a datasheet or source file commonly means the same thing.

For example, firmware gpio_put(PIN_RESET_N, 0) asserts reset and keeps the CPU from running. Writing 1 releases reset. HIGH means a valid voltage in that signal's domain, not always 5 V: the Z80 RESET# node is driven directly by a 3.3 V Pico output. Neither a HIGH reading nor a Hi-Z output means it is safe to connect that node to an arbitrary supply.

System and Processor Terms

Term	Meaning	Purpose in this project
SBC	Single-board computer	The complete Z80 computer built across the three breadboards.
Z80	Zilog 8-bit microprocessor family	Executes the monitor, test programs, and CP/M after the Pico loads SRAM.
CPU	Central processing unit	The Z84C0020PEC Z80 that executes program instructions.
Pico / Pico 2 W	Raspberry Pi Pico 2 W microcontroller board	Supervises startup, loads SRAM, traps I/O, provides virtual disks, and hosts the Wi-Fi terminal.
Supervisor	Controller responsible for safe startup and system management	Pico firmware owns reset, clock, assisted loading, trapped I/O, and faults.
Bus	Shared group of electrical signals	Carries addresses, data, or controls between Z80, SRAM, and buffered Pico interface.
Address bus / A0-A15	Sixteen wires selecting a memory location or I/O port	Addresses 65,536 byte locations; A0 is the least-significant bit and A15 the most-significant bit.
Data bus / D0-D7	Eight bidirectional wires carrying one byte	Transfers instruction, memory, and I/O data between devices.
Control bus	Timing and ownership signals such as MREQ#, RD#, and BUSACK#	Identifies the type and phase of each Z80 transaction.
I/O	Input/output	Communication with peripherals rather than ordinary memory. This design implements most peripherals in Pico firmware.
Port	An I/O address selected by a Z80 IN or OUT instruction	Selects terminal, disk, status, or other virtual-device registers.
Trap	Firmware interception of a Z80 I/O cycle	Stops the static Z80 clock so the Pico can inspect or complete the cycle.
Assisted loader	CPU-executed RAM loading	Pico injects LD HL,nn, LD (HL),n and LD A,(HL); Z80 alone drives addresses and writes.
DMA buffer	CP/M software transfer address	BIOS SETDMA selects a RAM buffer; it does not give Pico hardware bus-master capability.
ROMless	Having no physical Z80 ROM	Injected instructions populate SRAM, followed by a reset to execute the verified image.
Static CPU	CPU whose clock may be stopped without losing internal state	Allows the Pico to freeze the Z80 safely during a trapped I/O cycle.
Clock / CLK	Repeating timing signal	Advances the Z80 state machine; generated by the Pico and translated by the AHCT244.
Machine cycle	Group of clock periods used for one bus operation	Defines when addresses, controls, and data must become valid.
Wait state	Extra clock period inserted into a bus cycle	HCT32 WAIT holds I/O until GP9 releases it. Ordinary SRAM cycles have no added memory waits.

Memory, Storage, and Software Terms

Term	Meaning	Purpose in this project
RAM	Random-access memory	Read/write working memory; contents are normally lost when power is removed.
SRAM	Static random-access memory	U2 AS6C1008 provides two 64 KiB banks in a 128 KiB SRAM and needs no refresh clock.
Flash	Nonvolatile electrically erasable storage	Pico onboard flash holds firmware, the Z80 boot package, CP/M disks, and the write journal.
XIP	Execute in place	Pico address mapping that permits flash contents to be read like ordinary memory.
CP/M	Control Program for Microcomputers	The disk operating system run by the Z80.
BIOS	Basic Input/Output System	CP/M's board-specific layer for console and disk access. It is unrelated to a modern PC BIOS.
BDOS	Basic Disk Operating System	CP/M service layer implementing files, console functions, and other operating-system calls.
CCP	Console Command Processor	CP/M command interpreter that reads and runs commands.
DPB	Disk Parameter Block	CP/M table describing logical disk geometry and allocation rules.
LBA	Logical block address	Linear number identifying one 128-byte virtual-disk record.
Sector / record	Fixed-size disk transfer unit	CP/M exchanges one 128-byte record; flash updates preserve its containing 4 KiB erase sector.
Journal	Temporary recovery record written before changing disk data	Allows an interrupted flash write to recover the complete old or new block after reboot.
Manifest	Header describing an image and its integrity data	Gives boot-image length, version, and CRC values before SRAM loading.
CRC / CRC32	Cyclic redundancy check, using a 32-bit result here	Detects corruption in boot images, journal entries, and generated artifacts.
SHA-256	256-bit cryptographic hash	Records reproducible host-artifact identities; it is not calculated by the Z80.
Firmware	Software executed by a microcontroller	The phase-based Pico applications under src/.
Boot loader	Code that prepares and starts another program	Validates the flash package, copies the Z80 image to SRAM, then releases reset.
UF2	USB Flashing Format	Drag-and-drop or picotool firmware image format supported by Pico boot ROM.
BOOTSEL	Pico USB boot-selection mode	Allows firmware or complete flash images to be loaded while the application is not running.

Digital Electronics Terms

Term	Meaning	Purpose in this project
GPIO	General-purpose input/output	Individually programmable Pico pins used for clocks, controls, buses, and status.
PWM	Pulse-width modulation hardware	Pico peripheral generating the Z80 clock in non-PIO builds.
PIO	Programmable I/O hardware in the RP2350	In Phases 9 and 10, PIO0 generates the 20 MHz Z80 clock and the status OLED/speaker I2C; PIO1 completes every Z80 I/O cycle, including SRAM bank selects.
SIO	Single-cycle I/O block in the RP2350	Direct Pico GPIO hardware used for static levels and manual clock stepping; not Z80 serial I/O.
IRQ	Interrupt request	Hardware event that diverts Pico execution to the I/O trap handler.
ISR / handler	Interrupt service routine	Time-critical Pico function that freezes and services a trapped Z80 cycle.
OR gate	Output HIGH when either input is HIGH	HCT32 gates SRAM reads, WAIT release, and Pico-to-bus output.
Static hazard / glitch	Unwanted short output pulse caused by unequal logic delays	Must be checked at SRAM and CPU pins; a clean logical netlist does not prove analogue timing.
Buffer	Logic device that strengthens, isolates, or translates a signal	AHCT244 drives 5 V clock/control signals; LVC244 protects all eight monitored inputs.
Transceiver	Bidirectional or direction-controlled bus buffer	AHCT245 and LVC245 form separate Pico-to-bus and bus-to-Pico data paths.
Tri-state / high-impedance / Hi-Z	Output state that electrically disconnects its driver	Permits several devices to share a bus as long as only the intended owner drives it.
Bus contention	Two outputs driving different levels on one wire	Can damage parts. Firmware must disable both data paths before switching; RD gating is not an all-state interlock.
Level shifting / translation	Converting signals between voltage domains	Connects Pico 3.3 V logic to 5 V Z80, SRAM, and HCT32 without raw 5 V input paths.
5 V tolerant	Input may safely receive a specified 5 V-domain signal	Required for every path from installed 5 V logic into a 3.3 V-powered device.
Ioff	Partial-power-down input/output protection	Prevents LVC devices from being back-powered through their pins while their supply is off.
Pull-up / pull-down	Resistor weakly biasing a signal HIGH / LOW	Establishes a safe default when no active device drives the signal.
Decoupling / bypass capacitor	Small capacitor beside an IC supply pair	Supplies brief switching current locally and suppresses rail noise.
Bulk capacitor	Larger capacitor on a board or supply entry	Reduces slower supply dips; it does not replace local decoupling.
Power domain / rail	Group of devices sharing a supply voltage	The design has regulated 5 V logic and Pico-derived 3.3 V logic domains with common ground.
GND	Common electrical reference, nominally 0 V	Return path and voltage reference shared by all boards and instruments.
VCC / VDD	Positive IC supply voltage	Usually 5 V for Z80-side logic and 3.3 V for Pico-side LVC devices in this design.
VSYS / VBUS / 3V3	Pico system-input, USB 5 V, and regulated 3.3 V rails	Must be connected exactly as specified to avoid back-powering USB or the Pico regulator.
Schottky diode	Low-forward-voltage diode	The 1N5819 safely ORs external 5 V into Pico VSYS.

Signal Names and Bus Notation

The descriptions below state the signal's purpose when it is asserted. Because most Z80 controls are active LOW, an inactive signal normally sits HIGH.

Signal or notation	Meaning	Purpose in this project
CLK	Clock	Advances the Z80. The Pico generates it and the AHCT244 translates it to a compliant 5 V clock level.
RESET#	Reset	LOW initializes the Z80. It does not select any Pico memory controls.
BUSREQ#	Bus request	LOW asks the Z80 to float its buses for runtime flash quiescence, not Pico memory access.
BUSACK#	Bus acknowledge	LOW confirms the CPU bus grant before a flash erase/program operation.
MREQ#	Memory request	Z80 drives it LOW during a memory transaction; becomes the CPU-owned source for SRAM CE#.
IORQ#	Input/output request	Z80 drives it LOW during an I/O transaction; PIO or the firmware trap detects it to service the I/O cycle.
RD#	Read	Z80 drives it LOW when the selected memory or I/O device must place data onto D0-D7.
WR#	Write	Z80 drives it LOW when the selected memory or I/O device must accept data from D0-D7.
M1#	Machine-cycle-one	Z80 drives it LOW during an opcode fetch and interrupt acknowledgement; used here as a Phase 6 reset/fetch probe point.
RFSH#	Dynamic-memory refresh	Z80 output for refreshing DRAM after an opcode fetch; this SRAM design does not use it.
HALT#	Halt state	Z80 drives it LOW after executing HALT; not connected to the Pico in this design.
WAIT#	Wait request	HCT32 pin 6 computes IORQ# OR IO_RELEASE. GP9 remains HIGH until the I/O controls release. No WAIT pull-up is fitted.
INT#	Maskable interrupt request	An external device could pull it LOW to request a normal Z80 interrupt; unused and pulled HIGH here.
NMI#	Non-maskable interrupt request	A falling edge requests the Z80's highest-priority interrupt; unused and pulled HIGH here.
CE#	Chip enable	LOW selects SRAM; buffered CPU MREQ# is the only source.
CE2	Second chip-enable input	Active-HIGH SRAM enable tied permanently to 5 V; CE# remains the switched enable.
OE#	Output enable	LOW allows a memory, buffer, or transceiver to drive its output pins.
WE#	Write enable	LOW commands SRAM to store the current data-bus value.
DIR	Fixed transceiver direction	U9 DIR is +5 V; U10 DIR is GND. No firmware direction pin exists.
BOOT_READ_DISABLE	SRAM-read inhibit	GP5, buffered to HCT32, keeps SRAM OE# HIGH during injection.
IO_RELEASE	Independent WAIT release	GP9 allows the stalled I/O cycle to finish after data is ready.
PICO_DATA_UP_OE#	Output-enable request	GP6 OR raw RD# produces actual U9 DATA_UP_OE#.
DATA_UP_OE#	Actual Pico-to-bus enable	HCT32 pin 8 drives AHCT245 pin 19. LOW drives a byte only with RD# LOW.
DATA_DOWN_OE#	Bus-to-Pico enable	GP7 directly drives LVC245 pin 19. LOW receives CPU/SRAM data.
PICO_* / Z80_*	Source-name prefix	Distinguishes Pico-generated controls from Z80-generated controls in equations and net names.
A0-A15	Address bits 0 through 15	Shared 16-bit address bus; A0 is least significant and A15 most significant.
A16	SRAM address bit 16	Selected by GP8 through U4 AHCT244 to choose either 64 KiB SRAM bank.
D0-D7	Data bits 0 through 7	Shared 8-bit bidirectional data bus; D0 is least significant.
IN / OUT	Z80 input / output instructions	Read a byte from, or write a byte to, an I/O port serviced by Pico firmware or PIO.
#, _N, or overbar	Active-LOW notation	Indicates that LOW means asserted. For example, PIN_RD_N in source code represents hardware RD#.
X in a truth table	Don't-care value	Either LOW or HIGH is allowed because that input cannot alter the stated result.

Component Names and Pin Labels

The fitted IC references below match the current schematic and parts inventory. U5, U6, and U8 are not fitted.

Name or fragment	Meaning	Purpose in this project
Z84C0020PEC	Zilog CMOS Z80, 20 MHz grade, plastic DIP commercial part	U1: the specified CPU; the project breadboard has demonstrated 20 MHz operation.
AS6C1008-55PCN	Alliance Memory 128 KiB x 8 SRAM, 55 ns, plastic DIP	U2: provides 128 KiB as two selectable 64 KiB banks.
SN74HCT32N / HCT32	Quad OR gate with TTL-compatible inputs	U3: fixed boot-inhibit, WAIT-release, and data-strobe gating; HC32 is not a substitute.
SN74AHCT244N / AHCT244	8-channel non-inverting 5 V buffer with TTL inputs	U4: translates clock, bus request, boot inhibit, SRAM controls, and A16 bank select.
SN74AHCT245N / AHCT245	8-bit 5 V bus transceiver with TTL inputs	U9: implements the fixed Pico-to-5 V data path.
SN74LVC245AN / LVC245	8-bit low-voltage bus transceiver with 5 V-tolerant inputs	U10: implements the fixed 5 V-to-Pico data path.
SN74LVC244AN / LVC244	8-channel low-voltage buffer with 5 V-tolerant inputs	U7: buffers BUSACK/IORQ/RD/WR and A0/A1/A2/A4 into the Pico domain.
1N5819	Schottky rectifier diode	ORs external 5 V into Pico VSYS without feeding the USB VBUS node.
A1-A8 / B1-B8	The two eight-bit ports of a 245 transceiver	A faces the Pico and B faces the 5 V bus in this design.
1A1, 1Y1, etc.	Input and output labels on a 244 buffer bank	A is a buffer input and Y is its corresponding output; the leading digit selects a bank where present.
OE1# / OE2#	Output-enable inputs for buffer bank 1 / 2	Tied LOW on the always-readable LVC244 and AHCT244 buffers. A 245 transceiver instead has one OE# for all eight bits.
GP0, GP1, etc.	Pico general-purpose pin number	RP2350 GPIO index used by firmware; it is not the Pico header's physical pin number.
pin 1, notch, dot	Package orientation references	Identify how to insert a device without rotation or mirroring.
N, AN, PCN, PEC, PU, SP suffixes	Manufacturer package/grade codes	Distinguish exact orderable parts; consult that manufacturer's datasheet rather than assuming suffixes are interchangeable.

Pico Pad and Power Terms

Term	Meaning	Purpose in this project
RP2350	Microcontroller chip used by Pico 2 W	Executes the supervisor firmware and provides GPIO, PWM, flash access, and two CPU cores.
GP0-GP29	RP2350 GPIO numbers exposed or used by Pico 2 W	Firmware-level pin names; map them to physical header pins with the Pico header map.
Pad	Physical input/output cell on the RP2350 die	Determines electrical properties such as 5 V tolerance and ADC capability.
FT pad	Five-volt-tolerant digital pad	GP0-GP25 pad type; tolerance still depends on RP2350 power conditions.
ADC pad	Analog-to-digital-converter-capable pad	GP26-GP29 pad type; not 5 V tolerant, so GP27/GP28 monitors require the LVC244.
ADC	Analog-to-digital converter	Converts voltage to a number; not used for Z80 monitoring despite GP26-GP29 being ADC-capable.
IOVDD	RP2350 input/output supply	Must be present at 3.3 V for the FT-pad 5.5 V absolute-maximum condition to apply.
AGND	Pico analog ground pin	Bonded to common ground because this project does not use a separate analog subsystem.
ADC_VREF	Pico ADC reference-voltage pin	Left open because the project does not use Pico ADC measurements.
3V3 / 3V3(OUT)	Pico regulated 3.3 V output	Powers LVC244/LVC245 and 3.3 V pull-ups.
3V3_EN	Pico 3.3 V regulator enable	Left open; pulling it LOW would disable the Pico's 3.3 V rail.
RUN	Pico reset input	Left open; pulling it LOW resets the RP2350.
VBUS	USB connector's nominal 5 V node	Must not be tied to the external 5 V rail.
VSYS	Pico system power input	Receives external 5 V only through the 1N5819 and USB power through Pico's onboard diode.
Core 0 / Core 1	The two RP2350 processor cores	Core 0 owns timing and buses; core 1 owns USB, networking and runtime flash writes.
FIFO	First-in, first-out queue	Ordered communication buffer; the multicore FIFO is reserved by Pico flash lockout support.

Software, Network, File, and Test Abbreviations

Term	Meaning	Purpose in this project
SDK	Software development kit	Pico headers, libraries, tools, and build support used by the firmware.
API	Application programming interface	Defined functions through which code or tools access a subsystem.
CLI	Command-line interface	Text-based invocation of tools such as CMake, picotool, and test scripts.
CI	Continuous integration	Automated build/test environment that can reject boundary or artifact failures.
USB	Universal Serial Bus	Programs the Pico, carries diagnostics, and connects test instruments to the Mac.
UART	Universal asynchronous receiver/transmitter	Common serial protocol supported by decoders; the Z80 terminal itself is virtual, not a UART chip.
I2C / I²C	Inter-Integrated Circuit	Two-wire serial protocol connecting the Phase 10 status OLED and optional speaker to the Pico; not used for the CPU/SRAM interface.
TCP/IP	Transmission Control Protocol / Internet Protocol	Networking foundation used by HTTP and WebSocket traffic.
HTTP	Hypertext Transfer Protocol	Serves the browser terminal page from Pico default port 80, shared with WebSocket.
HTML	Hypertext Markup Language	Source format of the embedded browser terminal interface.
JSON	JavaScript Object Notation	Structured text format used for generated manifests.
CSV	Comma-separated values	Plain-text tabular export format for captures, measurements, and generated data.
SVG	Scalable Vector Graphics	Vector image format used for diagrams and schematic exports.
PDF	Portable Document Format	Generated printable edition of this specification and schematic.
FFT	Fast Fourier transform	Converts sampled time-domain data into a frequency spectrum.
DVM	Digital voltmeter	Instrument function that reports numeric voltage measurements.
RLE	Run-length encoding	Compression that stores repeated identical digital samples efficiently.
IEEE CRC32	Standard 32-bit CRC convention	Exact CRC algorithm used by boot and journal formats.
XIP_BASE	Base address of Pico's memory-mapped external flash	Added to a flash offset to obtain a readable pointer.
PICO_OK	Pico SDK success result	Required return from flash_safe_execute() before a flash operation is accepted.
watchdog	Hardware recovery timer	Reboots into journal recovery if runtime flash coordination cannot continue safely.
atomic	Operation observed as indivisible between cores	Protects shared status words without a lock needed by the trap.
nonblocking	Returns immediately rather than waiting	Required for trap hooks and foreground services that must not stall another critical task.
CRC, hash, verify	Different integrity checks	CRC detects transfer/storage corruption, SHA-256 identifies host artifacts, and verify compares programmed/read-back contents.

Units, Numeric Notation, and Data Sizes

Notation	Meaning	How to read it here
0x prefix	Hexadecimal (base-16) number	0xFF is decimal 255; convenient for bytes, addresses, masks, and register values.
bit	One binary digit	Has value 0 or 1. Eight bits form one byte.
byte	Eight bits	One Z80 data-bus transfer and one addressable SRAM location.
K, M, G in rates	Decimal kilo, mega, giga	Multipliers of 1,000; for example, 1 MHz is 1,000,000 cycles per second.
KiB / MiB	Kibibyte / mebibyte	Binary sizes of 1,024 bytes / 1,048,576 bytes.
KB / MB	Kilobyte / megabyte	Sometimes used informally in prose or vendor material; exact project image sizes are stated in bytes or KiB.
Hz, kHz, MHz	Hertz, kilohertz, megahertz	Cycles per second; used for clock, signal, and bandwidth values.
S/s, MS/s, GSa/s	Samples per second, mega-samples/s, giga-samples/s	Logic-analyzer or oscilloscope sampling rate, not signal frequency.
s, ms, us, ns	Second, millisecond, microsecond, nanosecond	Time units: each step is one thousand times smaller than the previous. Source identifiers use us for microseconds.
V, mV	Volt, millivolt	Electrical potential; 1 V equals 1,000 mV.
A, mA	Ampere, milliampere	Electrical current; 1 A equals 1,000 mA.
Ohm, kOhm	Ohm, kilo-ohm	Resistance; 10 kOhm means 10,000 ohms.
pF, nF, uF	Picofarad, nanofarad, microfarad	Capacitance units; adjacent steps differ by 1,000. uF is ASCII notation for µF.
Mpts, samples	Million points / recorded measurements	Capture-memory depth; available duration depends on sample rate and active channels.
x or ×	Multiplication or count	128K x 8 means 128K locations each eight bits wide; 8x10 kOhm means eight resistors.
1x / 10x	Probe attenuation	Probe delivers full voltage / one tenth voltage to the scope; software must use the matching setting.

Logic Families, Levels, and Timing

Term	Meaning	Purpose in this project
TTL	Transistor-transistor logic levels	A TTL-compatible input accepts a lower HIGH voltage than a 5 V CMOS input.
CMOS	Complementary metal-oxide-semiconductor logic	Technology used by the static Z80, SRAM, Pico, and most interface devices.
HCT	High-speed CMOS with TTL-compatible inputs	HCT32 implements SRAM-read inhibit, WAIT release, and upward data-enable gating. HC32 is not a substitute.
AHCT	Advanced high-speed CMOS with TTL-compatible inputs	AHCT244 translates clock, bus request, boot inhibit, and SRAM controls; AHCT245 drives the 5 V data bus from Pico 3.3 V outputs.
LVC	Low-voltage CMOS logic family	LVC244/LVC245 run at 3.3 V while accepting protected 5 V inputs.
HIGH / LOW	The two digital logic states	Voltage ranges, not exact voltages; valid limits are defined by each datasheet.
Assert / deassert	Make a control active / inactive	Independent of voltage wording; asserting RESET# means driving it LOW.
$V_{IH}$ / $V_{IL}$	Minimum input-HIGH / maximum input-LOW voltage	Determines whether a receiving input is guaranteed to recognize a signal.
$V_{OH}$ / $V_{OL}$	Guaranteed output-HIGH / output-LOW voltage	Determines whether a driver meets the receiving device's input thresholds under load.
Propagation delay	Time from input transition to output response	AHCT244/HCT32 delays and SRAM access constrain clock rate and sampling margin.
Setup time	Time data must be stable before a sampling clock edge	SRAM read data must arrive early enough for the Z80 to sample it correctly.
Hold time	Time data must remain stable after a sampling edge	Drivers must not release or change the bus too soon.
Rise / fall time	Time for a signal edge to change between LOW and HIGH	Fast edges, rather than only clock frequency, cause breadboard ringing and crosstalk.
Duty cycle	Percentage of a period that a signal is HIGH	The Z80 clock is targeted at 50%, with a stated acceptance range.
Ringing / overshoot	Oscillation or voltage excursion following an edge	Can cross logic thresholds or exceed ratings; checked with short-ground scope probing.
Crosstalk	Unwanted coupling from one signal into another	Reduced by short grouped wiring and nearby ground returns.
Timing margin	Remaining safe time or voltage beyond a required limit	Measured during qualification rather than inferred from part speed ratings alone.

Package, Construction, and Schematic Terms

Term	Meaning	Purpose in this project
IC	Integrated circuit	A packaged electronic device such as the Z80, SRAM, or logic buffer.
DIP / PDIP	Dual in-line package / plastic dual in-line package	Through-hole IC package with two parallel pin rows, suitable for sockets and breadboards.
Discrete resistor	One resistor in its own component body	The breadboard uses 40 individual 10 kOhm resistors, not packaged resistor networks.
Pin 1 / notch / dot	Package orientation marks	Prevent an IC from being inserted rotated or mirrored.
Breadboard ravine	Insulating center gap of a solderless breadboard	Separates the two IC pin rows so opposite pins are not shorted together.
Net	All electrically connected points sharing one signal name	Fundamental connection represented and checked in the KiCad schematic.
Junction	Explicit connection where wires meet	Distinguishes an intended shared node from crossing but unconnected wires.
ERC	Electrical rules check	KiCad check for incompatible, missing, or improperly driven schematic connections.
Netlist	Machine-readable list of components, pins, and nets	Independently compared with the generated manifest to validate schematic connectivity.
BOM	Bill of materials	List and quantity of components needed to build the system.

Measurement and Build Terms

Term	Meaning	Purpose in this project
Oscilloscope / scope	Instrument displaying voltage versus time	Measures analog levels, edge shape, pulse width, ringing, and timing between two signals.
Logic analyzer	Instrument recording many digital HIGH/LOW signals	The 16-channel DSLogic Plus correlates bus values and control ordering in repeated capture groups.
Buffer Mode	DSLogic mode that captures into onboard memory before uploading	Provides 100 MHz sampling with all 16 channels for project qualification captures.
Stream Mode	DSLogic mode that transfers samples continuously over USB	Extends duration, but all 16 channels are limited to 20 MHz and are unsuitable for 20 MHz timing qualification.
Input threshold	Voltage at which a logic analyzer changes its displayed digital state	DSLogic Plus provides a global adjustable threshold; it does not replace device-specific analogue $V_{IH}$/$V_{IL}$ checks.
RLE	Run-length encoding	Optional DSLogic compression for sparse Buffer Mode activity; disabled for fixed-depth baseline evidence.
MSO	Mixed-signal oscilloscope	Instrument combining analog scope channels with synchronized digital inputs; the DHO814 has four analog channels but no integrated digital bus inputs.
Probe	Instrument lead designed to minimize loading	A compensated 10x scope probe is used for analog measurements; logic probes capture digital states.
1x / 10x probe	Probe attenuation ratio	10x mode usually loads fast logic less and provides better bandwidth than 1x mode.
Ground spring	Very short probe-ground attachment	Prevents the probe's own ground-loop inductance from creating apparent ringing.
Bandwidth	Highest sine-wave frequency passed within a stated attenuation	The DHO814's 100 MHz front end has an approximate 3.5 ns calculated rise-time limit; with the supplied 150 MHz probe, the combined measurement-system limit is about 4.2 ns.
Sample rate	Number of measurements recorded per second	Determines time resolution; it is distinct from analog bandwidth.
Real-time sampling	Samples used for one displayed acquisition are collected from the same trigger event	The DHO814 uses real-time sampling, so Single mode can preserve a one-off transition for analysis.
Memory depth	Number of samples retained in one acquisition	The DHO814 provides up to 25 Mpts, allowing substantial pre-trigger and post-trigger context while retaining a useful sample rate.
AWG	Arbitrary waveform generator	Produces programmable test waveforms; available in many USB scopes but not required for Z80 operation.
SCPI	Standard Commands for Programmable Instruments	Text-command interface for automating compatible bench instruments.
KiCad	Electronic schematic and PCB design application	Holds the native electrical schematic and runs ERC.
CMake / Ninja	Build-system generator / build executor	Configure and compile the Pico firmware and generated CP/M artifacts.
Toolchain	Compiler, assembler, linker, libraries, and utilities	Converts source code into executable Pico and Z80 images.
Bare metal	Software running without a hosted desktop operating system	The Pico firmware links its own embedded runtime rather than macOS libraries.
lwIP	Lightweight IP networking stack	Supplies TCP/IP networking used by the Pico WebSocket terminal.
WebSocket	Persistent bidirectional browser/server connection	Carries terminal bytes between the browser and Pico with low overhead.