Power U4 from +5 V at pin 20, GND at pin 10, and tie enables pins 1/19 LOW.
Its TTL-compatible inputs accept Pico 3.3 V and Z80 TTL HIGH levels; its
outputs meet the SRAM CMOS-control and Z80 clock requirements. Use AHCT,
not AHC. Keep output pin 18 to Z80 CLK pin 6 short and local to the Core board.
These supply and ground connections are direct links, not resistors.
The local capacitors are additional to the direct supply/ground wires.
R24 is a separate 10 kOhm pull-down from Pico physical pin 11 (GP8) to GND;
U4 pin 17 and SRAM A16 pin 2 must not be directly grounded.
Done
Device
Pin / component
Required connection
U4 AHCT244
Pin 1, OE#
Common GND
U4 AHCT244
Pin 5, unused output
Leave open
U4 AHCT244
Pin 10, power GND
Common GND
U4 AHCT244
Pin 15, unused input
Common GND
U4 AHCT244
Pin 19, OE#
Common GND
U4 AHCT244
Pin 20, VCC
Core +5 V rail
U4 AHCT244
C4, 100 nF
Close to pin 20, between +5 V and nearby common GND
U3 HCT32
Pin 7, power GND
Common GND
U3 HCT32
Pin 11, unused output
Leave open
U3 HCT32
Pin 12, unused input
Common GND
U3 HCT32
Pin 13, unused input
Common GND
U3 HCT32
Pin 14, VCC
Memory +5 V rail
U3 HCT32
C3, 100 nF
Close to pin 14, between +5 V and nearby common GND
With power and USB disconnected, tick each row after checking continuity
at both actual socket contacts and isolation from adjacent pins. Progress
is saved in the Phase 2 checklist. Keep the CLK connection entirely on Core.