8. Progressive Build and Bring-Up Plan

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Scope: the three-BB830 breadboard prototype. Phase 0-10 below describe incremental socket installation, jumper wiring, and breadboard bring-up. The DIP and partial-SMT PCBs implement the same circuit, but each has its own BOM, mechanical assembly and 20 MHz qualification target. Do not substitute either PCB's placement or component packages into these breadboard installation steps.

Bring-up means proving a small part of the circuit works before adding the next part. Treat each phase like an integration test with a hardware fixture: the installed chips, wiring, firmware, and supply settings are all part of the test. A successful firmware upload alone does not prove the wiring.

Read the construction guide before handling the boards, then complete Phase 0 onward in order. Use the hardware pages as references, not as an instruction to wire and populate the whole computer at once. Prepare the firmware build tools before Phase 1; use the maintained phase programs rather than assembling displayed source files into your own test firmware.

Phase 4 includes the current SRAM A16 bank-select wiring and its power-off continuity checks. Phase 6 installs the SRAM and CPU, then qualifies both banks with the loader and CP/M tests.

For each phase:

1. Power off: disconnect external power and USB before moving a wire, inserting a chip, or using the meter's continuity mode.
2. Wire and inspect: follow that phase's wiring steps, verify chip orientation, then check each new connection end to end with a multimeter.
3. Power and test: use the specified current limit and firmware; measure the named signals with the appropriate instrument.
4. Record and decide: save the firmware version, rail voltages, idle current, test output, and any required captures. Advance only when every required test passes. If a result differs, stop at this phase and check the most recent wiring before changing firmware or adding more hardware.

A failing power check is a stop condition

A collapsed rail, unexpected current, or warm chip is not a software problem to debug while powered. Disconnect power first. Do not increase the current limit just to make the board start.

Phase sequence

Phase	Proves
0 - Power distribution	Sockets, rails, protection, and passive defaults
1 - Pico supervisor	Safe startup levels and GPIO routing
2 - Fixed logic and clock	HCT32 OR gates, buffered controls, clock quality
3 - Control and port monitor	Eight buffered inputs and independent WAIT release
4 - Address bus	Passive address-trunk wiring; CPU remains absent
5 - Data bus	Bidirectional translation and contention prevention
6 - Z80-assisted loading	Fit CPU/SRAM, qualify injection, run CPU/RAM diagnostics
CPU reset, fetch and bus grants	Phase 6 receiving-pin measurements and physical BUSREQ/BUSACK qualification
20 MHz arithmetic and SRAM soak	Optional one-hour resident CPU/stack/SRAM workload after earlier bring-up and frequency screens
No-I/O 20 MHz scope test	Separate continuous CPU/SRAM workload for scope captures; results retrieved from SRAM only after stopping
8 - Bidirectional I/O and USB terminal	IN replies, port aliases, terminal round-trip and repeated boot/I/O integration
9 - USB CP/M and flash storage	Controlled load/verify, 20 MHz scope-measured execution, USB terminal, all-record disk diagnostic and journal recovery
10 - WebSocket terminal	Final multicore network terminal and disk integration
Frequency qualification	Measured operating limit and complete timing evidence

The Phase 6 bus-grant diagnostic covers the CPU bus-grant checks; Phase 8 follows Phase 6.

Build and test one functional block at a time. Do not install the next chip until the current phase passes. Use sockets for all DIP devices, place a 100 nF ceramic capacitor directly across each IC's supply pins, and fit at least one 22 uF bulk capacitor per breadboard. Use a current-limited 5 V supply, multimeter, oscilloscope, and a DSLogic Plus logic analyzer using the documented capture groups. Start each first power-up of populated hardware at a 100 mA current limit. For the empty-board Phase 0 check, a regulated USB-C breadboard supply and multimeter are sufficient after the unpowered checks pass; adjustable current limiting is recommended extra protection. Remove power immediately if a rail falls by more than 5%, the supply's overcurrent indicator activates (if present), or a device becomes warm.

Each phase owns the signal wiring first required by that phase. Install and continuity-check those jumpers with the affected active devices removed, then insert only the devices named by the phase. The wiring diagrams are included from the consolidated hardware pages, which remain the authoritative subsystem references; the implementation plan presents the same source in construction order rather than maintaining duplicate diagrams.

Fit the specified pull-ups and pull-downs so every signal has its defined state before firmware starts. Use temporary 1 kOhm series resistors when first connecting two potentially driven nodes. Record idle current after each populated phase; Phase 0 needs only resistance and voltage readings. Unless stated otherwise, keep all chips from later phases out of their sockets.

Phase 1-10 embed the complete maintained applications and relevant shared modules in collapsed Maintained Source sections. Expand a file to read the code compiled by the firmware build; MkDocs includes it directly from src/ on every documentation build. Test plans include both existing diagnostic commands and manual measurements or test-only fault setups; they are not all automated. A command printing PASS does not replace the listed electrical checks. Record any test not performed as not verified, rather than inferring a pass.

Saved phase checklists

The Done boxes and inline checkboxes on Phase 0-10 save progress in your browser on this device. Each phase has its own Clear checklist button with confirmation; clearing one phase does not clear another. Progress is not synced across devices and is removed if you clear the site's browser data. If storage is blocked or full, a warning appears and the checkboxes still work without reliable saving.

Tick wiring/setup items only after completing their instructions, and tick test or pass-gate items only after measuring and recording the required result. A saved tick is a personal record, not automated verification, permission to skip a prerequisite, or evidence that hardware timing is qualified. Leave deferred, optional, or unperformed tests unticked.

The source index links the public headers, shared modules, and build definitions. Build each phase from the repository, not by compiling the displayed files as standalone programs.

PIN_BUSACK_N is GP0, driven from Z80 BUSACK# pin 23 through the SN74LVC244 input buffer. IORQ#, RD#, WR#, and A0/A1/A2/A4 use the same buffer, so no 5 V output reaches the Pico directly. GP5 is BOOT_READ_DISABLE, GP6/GP7 are active-low data enable requests, and GP9 independently releases WAIT. GP23 on the Pico 2 W is dedicated to the CYW43439 wireless module's control interface (shared with GP24/GP25/GP29) and must never be repurposed. PIN_DATA_0-PIN_DATA_7 occupy GP10-GP17. The CPU alone drives SRAM address and write controls; there is no memory-source selector. PIN_WR_N is GP28, buffered through the same SN74LVC244; io_trap_handler() reads both PIN_RD_N and PIN_WR_N to resolve cycle intent.